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Area 1

Advanced Gate Stack/Si Processing Science
(Chair: Y. Nara, Selete)

This subcommittee covers all the innovative front-end-ofline process technologies for advanced ilicon-based LSI devices. Papers are solicited in the following areas (but are not limited to these areas): (1) advanced gate stack technologies, such as a SiON gate insulator, high-k gate insulator, and metal gate technologies, including device integration technology; (2) front-end-of-line process technologies that break through the scaling limit, such as a low-temperature process, shallow junction formation, novel diffusion/oxidation, and high-precision etching; (3) reliability physics and analysis; and (4) characterization and modeling of a Si process.

Invited speakers:
"Advanced Gate Stack Technology ?Present Status and Challenges?" (tentative)
M. Niwa (Matsushita Electric, Japan)
"Current Status and Forecast toward hp45nm Node in CMOS Technology" (tentative)
T. Sugii (Fujitsu, Japan)
"Material and Process Characterization for Future CMOS Technology" (tentative)
S. Zaima (Nagoya Univ., Japan)

Area 2

Characterization and Materials Engineering for Device Integration
(Chair: S. Ogawa, Matsushita Electric)

In this session, technologies and sciences that cover a Si back-end-of-line process are discussed, including package technology. Low-k materials have been in practical use; however, they brought new, difficult issues with decreasing in size, especially in reliability and package areas, and these areas require different ideas from conventional interconnect in characterization, material, and process/structure technologies. Papers are solicited in the following areas (but are not limited to these areas): (1) characterization methodology for materials, mechanical and electrical properties in small geometry, and yield improvement; (2) materials and process technologies for advanced Cu/Low-k interconnect, including new dielectric and metal formation, planarization, and etching; (3) reliability phenomena and physics, such as EM, SIV, TDDB, and modeling/prediction; (5) packaging for Cu/Low-k chips; (4) new concepts and materials for future interconnects, such as a 3-D structure, a CNT interconnect, and wireless applications.

Invited speakers:
"Integration Challenges for Carbon Nanotubes"
F. Kreupl (Infineon, Germany)
"Cu/Low-k Process Integration for 65nm and 45nm SoC Devices"
N. Matsunaga (Toshiba, Japan)
"Nm-Order Structures of Porous Low-k Film and its Impact on Cu/Low-k Process"
M. Shimada (Selete, Japan)

Area 3

CMOS Devices/Device Physics
(Chair: K. Shibahara, Hiroshima Univ.)

The aim of this area is to discuss advanced silicon device technologies and physics. Papers are solicited in the following areas: (1) sub-100-nm silicon CMOS devices and their integration technologies; (2) performance enhancement technologies, such as a strained-silicon channel and SiGe and Ge channels; (3) post-bulk-planar silicon device structures, including planar SOI, FinFET, and double gate FET; (4) device physics of advanced CMOS, including simulation and modeling on carrier transport and reliability; and (5) manufacturing and yield science.

Invited speakers:
"Perspective on Emerging CMOS Devices and their Impact on Scaling Technologies" (tentative)
S. Biesemans (IMEC, Belgium)
"45nm Conventional Bulk and Bulk+ Architectures for Low Cost GP/LP Applications" (tentative)
F. Boeuf (ST Microelectronics, France)
"Investigation of NBTI in Ultra-Thin Oxide p-MOSFETs" (tentative)
S. Mahapatra (IIT Bombay, India)

Area 4

Advanced Memory Technology
(Chair: A. Nitayama, Toshiba)

Advanced memory technologies are very much expected to explosively evolve SoC devices and digital information technologies toward "high speed and high density, broadband and mobile." Papers are solicited in the area of all advanced volatile or nonvolatile memory devices, such as DRAM, flash (including SONOS and nanocrystal devices), FeRAM, MRAM, phase change RAM, resistance RAM, one time programming memory, 3-D memory, and others. Topics include cell device physics and characterization, process integration and materials, tunneling dielectrics, erroelectric and ferromagnetic materials, reliability, failure analysis, quality assurance and testing, modeling and simulation, process control and yield enhancement, integrated circuits, new concept memories, and new applications and systems (solid state disks, memory cards, programmable logic, etc.).

Invited speakers:
"Overview and Future Challenges of MONOS Technologies"
T. Ishimaru (Hitachi, Japan)
"Current Development Status and Future Challenge of FeRAM Technologies" (tentative)
S. Y. Lee (Samsung Electronics, Korea)
"Physical and Microscopic Understanding of Data Retention Time of DRAM"
K. Okonogi (Elpida, Japan)
"Overview and Future Challenge of MRAM Technologies"
S. Tehrani (Freescale, USA)

Area 5

Advanced Circuits and Systems
(Chair: H. Kobayashi, Gunma Univ.)

Original papers bridging the gap between materials, devices, circuits, and systems in Si-ULSI, including SiGe, are solicited in subject areas that include, but not limited to the following: (1) advanced digital, analog, mixedsignal circuits as well as memory; (2) high-speed and high-frequency circuits; (3) wireless, wireline, and optical communication; (4) power management technology; (5) interconnection design for communication inside a chip as well as among chips; (6) technologies for systems on a chip (SoC) and system in a package (SiP); and (7) LSI testing technology.

Invited speakers:
"Design and Architecture Exploration for Image and Video Coding Systems"
L.-G. Chen (National Taiwan Univ., Taiwan)
"Issues of Mixed-Signal Circuit Design in 90nm CMOS LSI Technology"
T. Iida (Toshiba, Japan)
"The High Voltage Anti-Trend"
C. Mangelsdorf (Analog Devices Inc., Japan)

Area 6

Compound Semiconductor Circuits, Electron Devices and Device Physics
(Chair: M. Kuzuhara, Univ. of Fukui)

This session covers all aspects of advanced electron device and IC technologies based on compound semiconductors, including III-V, III-N, SiC, and other materials. Papers are solicited in the following areas: (1) FETs, HFETs, HBTs, and other novel device structures; (2) high-voltage or high-temperature electron devices and circuits; (3) microwave and millimeter-wave amplifiers, oscillators, switches, and other ICs; (4) high-speed digital ICs and mixed-signal ICs; (5) theory and physics of electron devices; (6) characterization techniques for devices and ICs; (7) innovative device processing and packaging; (8) reliability issues; and (9) novel applications utilizing compound semiconductor devices and circuits. Contributions related to other interesting topics are also welcome.

Invited speakers:
"Insulated and Recessed Gate A1N/GaN/InN-based HEMTs on Different Substrates"
M. Shur (Rensselaer Polytechnic Inst., USA)
"Circuit Design for Super-Scaled InP HBTs" (tentative)
J. F. Jensen (Hughes Res. Labs., USA)
"Simulation of AlGaN/GaN Heterostructure Field Effect Transistors"
R. Mickevicius (Integrated Systems Engineering Inc., USA)
"Power Device Application of AlGaN/GaN HFETs on a Si Substrate"
T. Egawa (Nagoya Inst. of Tech., Japan)

Area 7

Photonic Devices and Device Physics
(Chair: M. Sugawara, Univ. of Tokyo)

The scope of this subcommittee covers all aspects of emerging technologies in active, passive, and integrated optoelectronic and photonic devices as well as device physics, which include: (1) laser diodes, LEDs, photodetectors, SOAs, and OEICs; (2) quantum nanostructure optical devices including quantum wells, quantum wires, or quantum dots; (3) photonic crystal materials and novel functional devices; (4) optical switches, modulators, and MEMS; (5) optical wavelength converters, nonlinear optical devices, and all-optical switches; (6) waveguide components, PLCs and integrated photonic circuits; (7) material and device processing and characterization techniques; (8) hybrid and monolithic integration, packaging and moduling; (9) optical communication, interconnection and signal processing applications of optoelectronic and photonic devices; (10) linear and nonlinear optical properties, electronic band structures, and the relaxation mechanism of quantum nanostructures; and (11) novel phenomena and applications including slow light, fast light, optical memory, and optoelectronic tweezers, etc.

Invited speakers:
"Recent Trend in High-Speed/Low-Power-Consumption Light Sources for MAN/Ethernet Applications"
M. Aoki (Hitachi, Japan)
"Slow Light Using Semiconductor Quantum Wells and Quantum Dots for Future Optical Networks"
S. L. Chuang (Univ. of Illinois at Urbana-Champaign, USA)
"Exciton-Photon Interactions in a Quantum Dot Microcavity"
A. Forchel (Univ. of Wuerzburg, Germany)

Area 8

Advanced Material Synthesis and Crystal Growth Technology
(Chair: H. Yamaguchi, NTT)

The scope of this subcommittee covers all kinds of synthesis, growth, and fabrication techniques of not only semiconducting but also novel functional materials and structures, including spintronic materials, nitride compounds, CNT, nanowires and nanoparticles, etc. The principle idea is to enhance mutual communication among people in different committees to share knowledge of commonly important key technologies in fabrication processes. Specific scopes are, but not limited to, the following: (1) novel material systems and structures; (2) materials and structures for spintronics; (3) nitride-related compound semiconductors; (4) novel synthesis, growth, and fabrication techniques; (5) carbon nanotubes; (6) nanowires and nanoparticles; (7) microscale- and nanoscale 3-D structures and mechanical systems; (8) characterization of fundamental properties.

Invited speakers:
"Revolution in Carbon Nanotube Synthesis ?Super Growth?"
D. Futaba (AIST, Japan)
"Quantum Dots, Quantum Dot Molecules, and Quantum Dot Crystals"
O.G. Schmidt (Max-Planck-Inst., Germany)
"Spintronics Based on ZnO Thin Films"
H. Tabata (Osaka Univ., Japan)
"To be announced"
Z. K. Tang (Hong Kong Univ. of Sci. & Tech., China)

Area 9

Physics and Applications of Novel Functional Materials and Devices
(Chair: Y. Takahashi, Hokkaido Univ.)

This session covers applications and physics of novel functional devices and quantum nanostructures that are made mainly by using nanofabrication technology or selforganized phenomena. Papers are solicited in the following areas (but are not limited to these areas): (1) quantum phenomena in nanostructures; (2) quantum dots and single-electron devices; (3) solid-state quantum computing and communications; (4) spintronics; (5) carbon nanotube devices; (6) nanometer-scale characterization, such as SPM and SNOM, other novel devices, such as small superconducting devices, and resonant tunneling devices in nanoscale.

Invited speakers:
"Manipulation and Storage of Charge and Spin in Quantum Dot Devices"
G. Abstreiter (Walter Schottky Inst., Germany)
"Fabrication and Demonstration of Quantum-Dot Cellular Automata Systems"
G. H. Bernstein (Univ. of Notre Dame, USA)
"Optical Spin-Detection of Quasi-2D Charge Carriers: Experimental Evidence of the Spin Hall
J. Wunderlich (Hitachi Cambridge Lab., UK)