Area 1

Advanced Gate Stack / Si Processing Science
(Chair: J. Yugami, Renesas Tech. Corp.)

This subcommittee covers all the innovative front-end-of-line process technologies and sciences for advanced silicon-based LSI devices. Not only the gate stack technology but all the new concepts on Si-based front-end process technologies are welcome. Papers are solicited in the following areas (but are not limited to these areas):(1) advanced gate stack technologies, such as a SiON gate insulator, high-k gate insulator, and metal gate technologies, including device integration technology; (2)front-end-of-line process technologies that break through the scaling limit, such as a low-temperature process, shallow junction formation, novel diffusion/oxidation, and high-precision etching; (3) reliability physics and analysis; and (4) characterization and modeling of a Si process.

Area 2

Characterization and Materials Engineering for Interconnect Integration
(Chair: Y. Hayashi, NEC Corp.)

Technologies and sciences that cover a Si back-end-of-line(BEOL) process are discussed, including package technology. Low-k materials have been in practical use; however, they brought new, difficult issues by scaling, especially in reliability and package areas. Innovations and new ideas are needed in the BEOL by introducing new materials with sophisticated characterization as well as novel BEOL process/structures with system integration points of view. Papers are solicited in the following areas: (1) characterization methodology for materials, mechanical and electrical properties in small geometry, metrology and yield improvement; (2) materials, process and packaging technologies for advanced Cu/Low-k interconnect; (3) reliability phenomena and physics, such as EM, SIV, TDDB, and modeling/prediction; (4) passive components for RF or High-speed operations; (5) new structures and materials on future interconnects, such as a 3-D structure, a CNT interconnect, an on-chip optical interconnect, and BEOL-based memory applications, i.e. MRAM, and PRAM.

Area 3

CMOS Devices /Device Physics
(Chair: M. Hane, NEC Corp.)

The aim of this area is to discuss advanced silicon device technologies and physics. Papers are solicited in the following areas: (1) sub-100-nm silicon CMOS devices and their integration technologies; (2) performance enhancement technologies, such as a strained-silicon channel or any high-mobility channels; (3) post-bulk-planar silicon device structures, including planar SOI, FinFET, multi-channels, or nano-wires; (4) device physics of advanced CMOS, including simulation and modeling on carrier transport and reliability; and (5) manufacturing and yield science in conjunction with the increasing variability of device parameters, fluctuations of fabrication parameters or the intrinsic atomistic nature.

Area 4

Advanced Memory Technology
(Chair: A. Nitayama, Toshiba Corp.)

Advanced memory technologies are very much expected to explosively evolve SoC devices and digital information technologies toward ‘‘high speed and high density, broadband and mobile.’’ Papers are solicited in the area of all advanced volatile or nonvolatile memory devices, such as DRAM, flash (including SONOS and nanocrystal devices), FeRAM, MRAM, phase change RAM, resistance RAM, one time programming memory, 3-D memory, and others. Topics include cell device physics and characterization, process integration and materials, tunneling dielectrics, ferroelectric and ferromagnetic materials, reliability, failure analysis, quality assurance and testing, modeling and simulation, process control and yield enhancement, integrated circuits, new concept memories, and new applications and systems (solid state disks, memory cards, programmable logic, etc.).

Area 5

Advanced Circuits and Systems
(Chair: S. Kawahito, Shizuoka Univ.)

Original papers bridging the gap between materials, devices, circuits, and systems in Si-ULSI, including SiGe, are solicited in subject areas that include, but not limited to the following; (1) advanced digital, analog, and mixed-signal circuits as well as memory; (2) high-speed and high-frequency circuits; (3) wireless, wireline, and optical communication circuits; (4) power devices and circuits as well as power management technology; (5)interconnection design for communication inside a chip as well as among chips; (6) technologies for systems on a chip (SoC) and system in a package (SiP); (7) LSI testing technology; (8) three-dimensional IC technology; (9)MEMS (passive) devices as well as circuits, RF MEMS;(10) sensor devices and circuits; (11) thin film transistors and circuits; and (12) organic devices and circuits.

Area 6

Compound Semiconductor Circuits, Electron Devices and Device Physics
(Chair: T. Hashizume, Hokkaido Univ.)

This session covers all aspects of advanced electron device and IC technologies based on compound semiconductors, including III-V, III-N, SiC, and other materials. Papers are solicited in the following areas: (1) FETs, HFETs, HBTs, and other novel device structures; (2) high-voltage or high-temperature electron devices and circuits; (3) microwave and millimeter-wave amplifiers, oscillators, switches, and other ICs; (4) high-speed digital ICs and mixed-signal ICs; (5) theory and physics of electron devices;(6) characterization techniques for devices and ICs; (7)innovative device processing and packaging; (8) reliability issues; and (9) novel applications utilizing compound semiconductor devices and circuits. Contributions related to other interesting topics are also welcome.

Area 7

Photonic Devices and Device Physics
(Chair: H. Yamada, Tohoku Univ.)

The scope of this subcommittee covers all aspects of emerging technologies in active, passive, and integrated optoelectronic and photonic devices as well as device physics, which include: (1) laser diodes, LEDs, photodetectors, SOAs, and OEICs; (2) quantum nanostructure optical devices including quantum wells, quantum wires, or quantum dots; (3) photonic crystal materials and novel functional devices; (4) optical switches, modulators, and MEMS; (5) optical wavelength converters, nonlinear optical devices, and all-optical switches; (6) waveguide components, PLCs and integrated photonic circuits; (7) material and device processing and characterization techniques; (8) hybrid and monolithic integration, packaging and moduling; (9) optical communication, interconnection and signal processing applications of optoelectronic and photonic devices;(10)linear and nonlinear optical properties, electronic band structures, and the relaxation mechanism of quantum nanostructures; and (11) novel phenomena and applications including slow light, fast light, optical memory, and optoelectronic tweezers, etc.

Area 8

Advanced Material Synthesis and Crystal Growth Technology
(Chair: A. Yamada, Tokyo Tech.)

The scope of this subcommittee covers all kinds of synthesis, growth, and fabrication techniques of not only semiconducting but also novel functional materials and structures, nitride compounds, CNT, nanowires and nanoparticles, etc. The principle idea is to enhance mutual communication among people in different committees to share knowledge of commonly important key technologies in fabrication processes. Specific scopes are, but not limited to, the following: (1) novel material systems and structures; (2) nitride-related compound semiconductors;(3) novel synthesis, growth, and fabrication techniques; (4) carbon nanotubes; (5) nanowires and nanoparticles; (6) microscale and nanoscale 3-D structures;(7) characterization of fundamental properties.

Area 9

Physics and Applications of Novel Functional Materials and Devices
(Chair: T. Fujisawa, NTT Corp.)

This session covers physics, applications and fabrication techniques of novel functional devices and quantum nanostructures. We strongly encourage novel, pioneering, and fundamental research works that would be influential in various solid state devices of various materials(semiconductors, metals, superconductors, magnetic and organic materials, etc.). Specific topics are (1) quantum phenomena in nanostructures; (2) quantum dots and single-electron devices; (3) resonant tunneling devices,(4) solid-state quantum computing and communications;(5) nanometer-scale characterization with spanning probe techniques; (6) nanofabrication techniques and self-organized phenomena; and (7) other novel devices, but are not limited to these subjects.